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2016-02-24Merge "MIPS32: Implement intrinsics from java.lang.Math:"Roland Levillain
2016-02-24Associate slow paths with the instruction that they belong to.David Srbecky
Almost all slow paths already know the instruction they belong to, this CL just moves the knowledge to the base class as well. This is needed to be be able to get the corresponding dex pc for slow path, which allows us generate better native line numbers, which in turn fixes some native debugging stepping issues. Change-Id: I568dbe78a7cea6a43a4a71a014b3ad135782c270
2016-02-24Merge "Remove HNativeDebugInfo from start of basic blocks."David Srbecky
2016-02-24Remove HNativeDebugInfo from start of basic blocks.David Srbecky
We do not require full environment at the start of basic block. The dex pc contained in basic block is sufficient for line mapping. Change-Id: I5ba9e5f5acbc4a783ad544769f9a73bb33e2bafa
2016-02-22MIPS32: Implement intrinsics from java.lang.Math:Chris Larsen
- abs(double) - abs(float) - abs(int) - abs(long) - max(double, double) - max(float, float) - max(int, int) - max(long, long) - min(double, double) - min(float, float) - min(int, int) - min(long, long) - sqrt(double) The math intrinsics: - ceil(double) - floor(double) - rint(double) - round(double) - round(float) aren't implemented because they require instructions which only exist for MIPS64, or for MIPS32r6. Change-Id: I943be3592b52a423fcb7ac40f46f38a5e2a58c50
2016-02-17Fix uses of art::HCompare::IsGtBias on MIPS32 and MIPS64.Roland Levillain
Do not call this method on non floating-point HCompare instructions. Change-Id: I262ab23f48d32295641063f897dca02cb92eb2e2
2016-02-17Merge "MIPS32: peek*/poke*, and String.charAt intrinsics."Roland Levillain
2016-02-12ART: Remove HTemporaryDavid Brazdil
Change-Id: I21b984224370a9ce7a4a13a9652503cfb03c5f03
2016-02-10MIPS32: peek*/poke*, and String.charAt intrinsics.Chris Larsen
- byte libcore.io.Memory.peekByte(long address) - short libcore.io.Memory.peekShort(long address) - int libcore.io.Memory.peekInt(long address) - long libcore.io.Memory.peekLong(long address) - void libcore.io.Memory.pokeByte(long address, byte value) - void libcore.io.Memory.pokeShort(long address, short value) - void libcore.io.Memory.pokeInt(long address, int value) - void libcore.io.Memory.pokeLong(long address, long value) - char java.lang.String.charAt(int index) Change-Id: I5ff30b61d87313d00f0fd3f0ee09f1c454f9c9fa
2016-02-05Implemented compare/signum intrinsics as HCompareAart Bik
(with all code generation for all) Rationale: At HIR level, many more optimizations are possible, while ultimately generated code can take advantage of full semantics. Change-Id: I6e2ee0311784e5e336847346f7f3c4faef4fd17e
2016-02-03Merge "Implement first kind of polymorphic inlining on MIPS."Roland Levillain
2016-02-03Implement first kind of polymorphic inlining on MIPS.Roland Levillain
Change-Id: Ie430d6c5821273143a1872b376e8e24683d00ab0
2016-02-02MIPS32: Fix codegen register dumps.Vladimir Marko
Dump raw registers instead of managed registers to be in line with other architectures. This fixes a checker failure in 510-checker-try-catch where we have previously emitted a space that stopped the regexp search. However, there still remains a runtime failure of the 510 test: Exception in thread "main" java.lang.Error: Method: "testCatchPhi_double", path: ExceptionalFlow1, expected: 3, actual: 0 Change-Id: Ib9ad2c60baf2e322ce1eb58b9dc39feb5ab6f148
2016-01-29ART: Do not use AT register in MIPS DSS<->RP swapDavid Brazdil
LoadFromOffset clobbers AT if stack offset does not fit in int16_t. We should never hit that limit but let's stay on the safe side. Change-Id: I77f564dc3edd0b47d06f8fafb5610c7c0205e9b2
2016-01-28ART: Add missing swaps to MIPS codegenDavid Brazdil
Change-Id: I0fb50280ddf43f817d991c15d3b6cdeb4635d6c2
2016-01-28Merge "Implement first kind of polymorphic inlining."Nicolas Geoffray
2016-01-28Implement first kind of polymorphic inlining.Nicolas Geoffray
Add HClassTableGet to fetch an ArtMethod from the vtable or imt, and compare it to the only method the profiling saw. Change-Id: I76afd3689178f10e3be048aa3ac9a97c6f63295d
2016-01-28ART: Implement HSelectDavid Brazdil
This patch adds a new HIR instruction to Optimizing. HSelect returns one of two inputs based on the outcome of a condition. This is only initial implementation which: - defines the new instruction, - repurposes BooleanSimplifier to emit it, - extends InstructionSimplifier to statically resolve it, - updates existing code and tests accordingly. Code generators currently emit fallback if/then/else code and will be updated in follow-up CLs to use platform-specific conditional moves when possible. Change-Id: Ib61b17146487ebe6b55350c2b589f0b971dcaaee
2016-01-28ART: Implement support for instruction inliningDavid Brazdil
Optimizing HIR contains 'non-materialized' instructions which are emitted at their use sites rather than their defining sites. This was not properly handled by the liveness analysis which did not adjust the use positions of the inputs of such instructions. Despite the analysis being incorrect, the current use cases never produce incorrect code. This patch generalizes the concept of inlined instructions and updates liveness analysis to set the compute use positions correctly. Change-Id: Id703c154b20ab861241ae5c715a150385d3ff621
2016-01-18ART: Remove Baseline compilerDavid Brazdil
We don't need Baseline any more and it hasn't been maintained for a while anyway. Let's remove it. Change-Id: I442ed26855527be2df3c79935403a25b1ee55df6
2016-01-15Merge "ART: Remove incorrect HFakeString optimization"David Brazdil
2016-01-14ART: Remove incorrect HFakeString optimizationDavid Brazdil
Simplification of HFakeString assumes that it cannot be used until String.<init> is called which is not true and causes different behaviour between the compiler and the interpreter. This patch removes the optimization together with the HFakeString instruction. Instead, HNewInstance is generated and an empty String allocated until it is replaced with the result of the StringFactory call. This is consistent with the behaviour of the interpreter but is too conservative. A follow-up CL will attempt to optimize out the initial allocation when possible. Bug: 26457745 Bug: 26486014 Change-Id: I7139e37ed00a880715bfc234896a930fde670c44
2016-01-14Merge "MIPS32: don't use R2+ instructions (mthc1, mfhc1) on MIPS32R1 or with ↵Roland Levillain
32-bit FPUs."
2016-01-14Merge "MIPS: Improve conversion between ints and floats."Roland Levillain
2016-01-13MIPS32: don't use R2+ instructions (mthc1, mfhc1) on MIPS32R1 orAlexey Frunze
with 32-bit FPUs. Change-Id: If66932fb39cdd5946f6c05c82036191ad405a877
2016-01-13MIPS: Improve conversion between ints and floats.Alexey Frunze
Change-Id: I767fe9623cc14e8480c31e305725eb5221cac282
2016-01-13MIPS: HRor clean-upAlexey Frunze
This is a follow up to https://android-review.googlesource.com/#/c/194590/. Change-Id: Ia37faa02736e5dd54c1e71fd2a4d94e074746757
2016-01-13Merge "Reduce code size by sharing slow paths."Aart Bik
2016-01-13Merge "MIPS: Implement HRor"Vladimir Marko
2016-01-12Reduce code size by sharing slow paths.Aart Bik
Rationale: Sharing identical slow path code reduces code size. Background: Currently, slow paths with the same dex-pc, same physical register spilling code, and identical stack maps are shared (making this only useful for deopt slow paths). The newly introduced mechanism is sufficiently general to allow future improvements by e.g. allowing different dex-pc (by passing this to runtime) or even the kind of slow paths (by passing runtime addresses to the slowpath). Change-Id: I819615c47b4fd98440a241f681f93e4fc22d12e0
2016-01-11Merge "Generate Nops to ensure that debug stack maps have distinct PC."David Srbecky
2016-01-11Merge "Don't use std::abs on INT_MIN/LONG_MIN, it's undefined."Nicolas Geoffray
2016-01-11Generate Nops to ensure that debug stack maps have distinct PC.David Srbecky
Change-Id: I5740ec958a20d236634b66df0e675382ed5c16fc
2016-01-11Don't use std::abs on INT_MIN/LONG_MIN, it's undefined.Nicolas Geoffray
bug:25494265 Change-Id: I560a3a589b92440020285f9adfdf7c9efb06217c
2016-01-04MIPS: Implement HRorAlexey Frunze
This also fixes differentiation between the SRL and ROTR instructions in the disassembler. Change-Id: Ie19697f8d6ea8fa4e338adde3e3cf8e4a0383eae
2016-01-04Merge "MIPS32: improvements in code generation (mostly 64-bit ALU ops)"Nicolas Geoffray
2015-12-23Generate more stack maps during native debugging.David Srbecky
Generate extra stack map at the start of each java statement. The stack maps are later translated to DWARF which allows LLDB to set breakpoints and view local variables. Change-Id: If00ab875513308e4a1399d1e12e0fe8934a6f0c3
2015-12-23Rewrite HInstruction::Is/As<type>().Vladimir Marko
Make Is<type>() and As<type>() non-virtual for concrete instruction types, relying on GetKind(), and mark GetKind() as PURE to improve optimization opportunities. This reduces the number of relocations in libart-compiler.so's .rel.dyn section by ~4K, or ~44%, and in .data.rel.ro by ~18K, or ~65%. The file is 96KiB smaller for Nexus 5, including 8KiB reduction of the .text section. Unfortunately, the g++/clang++ __attribute__((pure)) is not strong enough to avoid duplicated virtual calls and we would need the C++ [[pure]] attribute proposed in n3744 instead. To work around this deficiency, we introduce an extra non-virtual indirection for GetKind(), so that the compiler can optimize common expressions such as instruction->IsAdd() || instruction->IsSub() or instruction->IsAdd() && instruction->AsAdd()->... which contain two virtual calls to GetKind() after inlining. Change-Id: I83787de0671a5cb9f5b0a5f4a536cef239d5b401
2015-12-17Merge "Revert "Revert "ART: Reduce the instructions generated by packed ↵Vladimir Marko
switch."""
2015-12-17Revert "Revert "ART: Reduce the instructions generated by packed switch.""Vladimir Marko
This reverts commit b4c137630fd2226ad07dfd178ab15725374220f1. The underlying issue was fixed by https://android-review.googlesource.com/188271 . Bug: 26121945 Change-Id: I58b08eb1a9f0a5c861f8cda93522af64bcf63920
2015-12-16MIPS32: improvements in code generation (mostly 64-bit ALU ops)Alexey Frunze
Specifically: - Use the delay slot in InvokeRuntime() for direct entry points - Use kNoOutputOverlap wherever possible - Improve and/or/xor/add/sub with 64-bit integer constants - Improve 64-bit shifts by a constant amount on R2+ - More efficient load/store of 64-bit constants (especially, 0 & +0.0) Change-Id: I86d2217c8b5b8e2a9371effc2ce38b9eec62782b
2015-12-16Remove spurious references to kEmitCompilerReadBarrier in MIPS.Roland Levillain
We do not support read barriers on MIPS code generators yet. Also, wrap some long lines in the MIPS64 code generator. Change-Id: Ia2755590afa60eb9c8fb547e059146ab6518372b
2015-12-16Merge "MIPS32: Fuse long and FP compare & condition in Optimizing."Roland Levillain
2015-12-16Merge "Revert "ART: Reduce the instructions generated by packed switch.""Nicolas Geoffray
2015-12-16Revert "ART: Reduce the instructions generated by packed switch."Nicolas Geoffray
This reverts commit 59f054d98f519a3efa992b1c688eb97bdd8bbf55. bug:26121945 Change-Id: I8a5ad7ef1f1de8d44787c27528fa3f7f5c2e9cd3
2015-12-15MIPS32: Fuse long and FP compare & condition in Optimizing.Alexey Frunze
This also does a minor clean-up in the assembler and its test. Bug: 25559148 Change-Id: I9bad3c500b592a09013b56745f70752eb284a842
2015-12-11Merge "Replace rotate patterns and invokes with HRor IR."Vladimir Marko
2015-12-11Replace rotate patterns and invokes with HRor IR.Scott Wakeling
Replace constant and register version bitfield rotate patterns, and rotateRight/Left intrinsic invokes, with new HRor IR. Where k is constant and r is a register, with the UShr and Shl on either side of a |, +, or ^, the following patterns are replaced: x >>> #k OP x << #(reg_size - k) x >>> #k OP x << #-k x >>> r OP x << (#reg_size - r) x >>> (#reg_size - r) OP x << r x >>> r OP x << -r x >>> -r OP x << r Implemented for ARM/ARM64 & X86/X86_64. Tests changed to not be inlined to prevent optimization from folding them out. Additional tests added for constant rotate amounts. Change-Id: I5847d104c0a0348e5792be6c5072ce5090ca2c34
2015-12-10Don't generate a slow path for strings in the dex cache.Nicolas Geoffray
Change-Id: I1d258f1a89bf0ec7c7ddd134be9215d480f0b09a
2015-12-10Merge "MIPS32: Improve integer division by constants"Nicolas Geoffray
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