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path: root/compiler/optimizing/code_generator.h
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2015-09-14Revert "ART: Register allocation and runtime support for try/catch"David Brazdil
Breaks libcore test org.apache.harmony.security.tests.java.security.KeyStorePrivateKeyEntryTest#testGetCertificateChain. Need to investigate. This reverts commit b022fa1300e6d78639b3b910af0cf85c43df44bb. Change-Id: Ib24d3a80064d963d273e557a93469c95f37b1f6f
2015-09-14ART: Register allocation and runtime support for try/catchDavid Brazdil
This patch completes a series of CLs that add support for try/catch in the Optimizing compiler. With it, Optimizing can compile all methods containing try/catch, provided they don't contain catch loops. Future work will focus on improving performance of the generated code. SsaLivenessAnalysis was updated to propagate liveness information of instructions live at catch blocks, and to keep location information on instructions which may be caught by catch phis. RegisterAllocator was extended to spill values used after catch, and to allocate spill slots for catch phis. Catch phis generated for the same vreg share a spill slot as the raw value must be the same. Location builders and slow paths were updated to reflect the fact that throwing an exception may not lead to escaping the method. Instruction code generators are forbidden from using of implicit null checks in try blocks as live registers need to be saved before handing over to the runtime. CodeGenerator emits a stack map for each catch block, storing locations of catch phis. CodeInfo and StackMapStream recognize this new type of stack map and store them separate from other stack maps to avoid dex_pc conflicts. After having found the target catch block to deliver an exception to, QuickExceptionHandler looks up the dex register maps at the throwing instruction and the catch block and copies the values over to their respective locations. The runtime-support approach was selected because it allows for the best performance in the normal control-flow path, since no propagation of catch phi values is necessary until the exception is thrown. In addition, it also greatly simplifies the register allocation phase. ConstantHoisting was removed from LICMTest because it instantiated (now abstract) HConstant and was bogus anyway (constants are always in the entry block). Change-Id: Ie31038ad8e3ee0c13a5bbbbaf5f0b3e532310e4e
2015-09-03Add more dwarf debug line info for Optimized methods.Yevgeny Rouban
Optimizing compiler generates minimum debug line info that is built using the dex_pc information about suspend points. This is not enough for performance and debugging needs. This CL generates additional debug line information for instructions which have known dex_pc and it ensures that whole call sites are mapped (as opposed to suspend points which map only one instruction past the function call). Bug: 23157336 Change-Id: I9f2b1c2038e3560847c175b8121cf9496b8b58fa Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
2015-09-02Optimizing: Tag Arena allocations with their source.Vladimir Marko
This adds the ability to track where we allocate memory when the kArenaAllocatorCountAllocations flag is turned on. Also move some allocations from native heap to the Arena and remove some unnecessary utilities. Bug: 23736311 Change-Id: I1aaef3fd405d1de444fe9e618b1ce7ecef07ade3
2015-08-27Add OptimizingCompilerStats to the CodeGenerator class.Serban Constantinescu
Just refactoring, not yet used, but will be used by the incoming patch series and future CodeGen specific stats. Change-Id: I7d20489907b82678120518a77bdab9c4cc58f937 Signed-off-by: Serban Constantinescu <serban.constantinescu@linaro.org>
2015-08-27Use CodeGenerator::RecordPcInfo instead of SlowPathCode::RecordPcInfo.Serban Constantinescu
Part of a clean-up and refactoring series. SlowPathCode::RecordPcInfo is currently just a wrapper around CodGenerator::RecordPcInfo. Change-Id: Iffabef4ef37c365051130bf98a6aa6dc0a0fb254 Signed-off-by: Serban Constantinescu <serban.constantinescu@linaro.org>
2015-08-19Revert "Revert "Optimizing: Better invoke-static/-direct dispatch.""Vladimir Marko
Fixed kCallArtMethod to use correct callee location for kRecursive. This combination is used when compiling with debuggable flag set. This reverts commit b2c431e80e92eb6437788cc544cee6c88c3156df. Change-Id: Idee0f2a794199ebdf24892c60f8a5dcf057db01c
2015-08-19Revert "Optimizing: Better invoke-static/-direct dispatch."Vladimir Marko
Reverting due to failing ndebug tests. This reverts commit 9b688a095afbae21112df5d495487ac5231b12d0. Change-Id: Ie4f69da6609df3b7c8443412b6cf7f5c43c2c5d9
2015-08-19Optimizing: Better invoke-static/-direct dispatch.Vladimir Marko
Add framework for different types of loading ArtMethod* and code pointer retrieval. Implement invoke-static and invoke-direct calls the same way as Quick. Document the dispatch kinds in HInvokeStaticOrDirect's new enumerations MethodLoadKind and CodePtrLocation. PC-relative loads from dex cache arrays are used only for x86-64 and arm64. The implementation for other architectures will be done in separate CLs. Change-Id: I468ca4d422dbd14748e1ba6b45289f0d31734d94
2015-08-12Add a GVN dependency 'GC' for garbage collection.Alexandre Rames
This will be used by incoming architecture specific optimizations. The dependencies must be conservative. When an HInstruction is created we may not be sure whether it can trigger GC. In that case the 'ChangesGC' dependency must be set. We control at code-generation time that HInstructions that can call have the 'ChangesGC' dependency set. Change-Id: Iea6a7f430009f37a9599b0a0039207049906e45d
2015-08-07Ensure coherency of call kinds for LocationSummary.Alexandre Rames
The coherency is enforced with checks added in the `InvokeRuntime` helper, that we now also use on x86 and x86_64. Change-Id: I8cb92b042f25dc3c5fd390e9c61a45b477d081f4
2015-07-06Revert "Revert "Fix LSRA bug with explicit register temporaries""Nicolas Geoffray
This reverts commit a5fc140ff315dda9bc0a8e59963ed547676cd941. Change-Id: Ic322484176e55d0c7cd7250d629b9e5046006a4f
2015-07-06Revert "Fix LSRA bug with explicit register temporaries"Calin Juravle
register_allocator_test32 fails. This reverts commit 283b8541546e7673d33d104241623d07c91cf500. Change-Id: I2a46f3c68de3e8273e402102065c13797045c481
2015-07-06Fix LSRA bug with explicit register temporariesMark Mendell
A temporary with an explicit RegisterLocation, such as ESI on x86 didn't have the register marked as allocated. This caused it to not be saved/restored in the prologue/epilogue, causing problems in the caller routine, which expected it to be saved. Found while implementing https://android-review.googlesource.com/#/c/157522/. Change-Id: I22ca2b24c2d21b1c6ab6cfb7dec26cb38034a891 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-06-22Opt compiler: Add disassembly to the '.cfg' output.Alexandre Rames
This is automatically added to the '.cfg' output when using the usual `--dump-cfg` option. Change-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb
2015-06-19Opt compiler: Add a description to slow paths.Alexandre Rames
Change-Id: I22160d90de3fe0ab3e6a2acc440bda8daa00e0f0
2015-06-17Revert "Revert "ART: Implement literal pool for arm, fix branch fixup.""Vladimir Marko
This reverts commit fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98. Adjust block label positions. Bad catch block labels were the reason for the revert. Change-Id: Ia6950d639d46b9da6b07f3ade63ab46d03d63310
2015-06-16Revert "ART: Implement literal pool for arm, fix branch fixup."Vladimir Marko
This reverts commit f38caa68cce551fb153dff37d01db518e58ed00f. Change-Id: Id88b82cc949d288cfcdb3c401b96f884b777fc40 Reason: broke the tests.
2015-06-15ART: Implement literal pool for arm, fix branch fixup.Vladimir Marko
Change-Id: Iecc91418bb4ee1c957f42fefb737d0ee2ba960e7
2015-06-12Optimizing: Remove PcInfo, use the StackMapStream instead.Vladimir Marko
Change-Id: I474f3a89f6c7ee5c7accd21791b1c1e311104158
2015-06-03Factorize code for common LocationSummary of HInvoke.Nicolas Geoffray
This is one step forward, we could factorize more, but I wanted to get this out of the way first. Change-Id: I6ae411a737eebaecb64974f47af507ce0cfbae85
2015-05-29Move mirror::ArtMethod to nativeMathieu Chartier
Optimizing + quick tests are passing, devices boot. TODO: Test and fix bugs in mips64. Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS. Some of the savings are from removal of virtual methods and direct methods object arrays. Bug: 19264997 Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d
2015-05-18Merge "Opt compiler: ARM64: Use ldp/stp on arm64 for slow paths."Nicolas Geoffray
2015-05-18Merge "Support InlineInfo in StackMap."Nicolas Geoffray
2015-05-18Support InlineInfo in StackMap.Nicolas Geoffray
Change-Id: I9956091775cedc609fdae7dec1433fcb8858a477
2015-05-13[optimizing] Fold HTypeConversion of constantsMark Mendell
While looking into optimizing long shifts on x86, I found that the compiler wasn't folding HTypeConversion of constants. Add simple conversions of constants, taking care of float/double values with NaNs and small/large values, ensuring Java conversion semantics. Add checker cases to see that constant folding of HTypeConversion is done. Ensure 422-type-conversion type conversion routiness don't get inlined to avoid compile time folding. Change-Id: I5a4eb376b64bc4e41bf908af5875bed312efb228 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-04-29Factor MoveArguments methods in Optimizing's intrinsics handlers.Roland Levillain
Also add a precondition similar to the one present in code generators, regarding static invoke related explicit clinit check elimination in non-baseline compilations. Change-Id: I26f4dcb5d02824d7556f90b4b0c85b08b737fa53
2015-04-29Refactor InvokeDexCallingConventionVisitor in Optimizing.Roland Levillain
Change-Id: I7ede0f59d5109644887bf5d39201d4e1bf043f34
2015-04-28Have HInvoke instructions know their number of actual arguments.Roland Levillain
Add an art::HInvoke::GetNumberOfArguments routine so that art::HInvoke and its subclasses can return the number of actual arguments of the called method. Use it in code generators and intrinsics handlers. Consequently, no longer remove a clinit check as last input of a static invoke if it is still present during baseline code generation, but ensure that static invokes have no such check as last input in optimized compilations. Change-Id: Iaf9e07d1057a3b15b83d9638538c02b70211e476
2015-04-24Opt compiler: ARM64: Use ldp/stp on arm64 for slow paths.Zheng Xu
It should be a bit faster than load/store single registers and reduce the code size. Change-Id: I67b8302adf6174b7bb728f7c2afd2c237e34ffde
2015-04-15Type MoveOperands.Nicolas Geoffray
The ParallelMoveResolver implementation needs to know if a move is for 64bits or not, to handle swaps correctly. Bug found, and test case courtesy of Serguei I. Katkov. Change-Id: I9a0917a1cfed398c07e57ad6251aea8c9b0b8506
2015-04-09Implement CFI for Optimizing.David Srbecky
CFI is necessary for stack unwinding in gdb, lldb, and libunwind. Change-Id: I1a3480e3a4a99f48bf7e6e63c4e83a80cfee40a2
2015-03-24Unify ART's various implementations of bit_cast.Roland Levillain
ART had several implementations of art::bit_cast: 1. one in runtime/base/casts.h, declared as: template <class Dest, class Source> inline Dest bit_cast(const Source& source); 2. another one in runtime/utils.h, declared as: template<typename U, typename V> static inline V bit_cast(U in); 3. and a third local version, in runtime/memory_region.h, similar to the previous one: template<typename Source, typename Destination> static Destination MemoryRegion::local_bit_cast(Source in); This CL removes versions 2. and 3. and changes their callers to use 1. instead. That version was chosen over the others as: - it was the oldest one in the code base; and - its syntax was closer to the standard C++ cast operators, as it supports the following use: bit_cast<Destination>(source) since `Source' can be deduced from `source'. Change-Id: I7334fd5d55bf0b8a0c52cb33cfbae6894ff83633
2015-03-17ART: Fix condition for StoreNeedsWriteBarrierDavid Brazdil
Codegen's StoreNeedsWriteBarrier assumed nulls are represented as integer constants and generated a barrier when not needed. This patch fixes the bug. Change-Id: I79247f1009b1fe6f24dba0d57e846ecc55806d4d
2015-03-16Update locations of registers after slow paths spilling.Nicolas Geoffray
Change-Id: Id9aafcc13c1a085c17ce65d704c67b73f9de695d
2015-03-13Merge "[optimizing] Don't record None locations in the stack maps."Nicolas Geoffray
2015-03-13[optimizing] Don't record None locations in the stack maps.Nicolas Geoffray
- moved environment recording from code generator to stack map stream - added creation/loading factory methods for the DexRegisterMap (hides internal details) - added new tests Change-Id: Ic8b6d044f0d8255c6759c19a41df332ef37876fe
2015-03-13Refactor code in preparation of correct stack maps in slow path.Nicolas Geoffray
Move the logic of saving/restoring live registers in slow path in the SlowPathCode method. Also add a RecordPcInfo helper to SlowPathCode, that will act as the placeholder of saving correct stack maps. Change-Id: I25c2bc7a642ef854bbc8a3eb570e5c8c8d2d030c
2015-03-11Revert "Revert "[optimizing] Enable x86 long support.""Nicolas Geoffray
This reverts commit 154552e666347d41d95d7619c6ee56249ff4feca. Change-Id: Idc726551c249a888b7ff5fde8508ae50e81b2e13
2015-03-06Revert "[optimizing] Enable x86 long support."Nicolas Geoffray
Few libcore failures. This reverts commit b4ba354cf8d22b261205494875cc014f18587b50. Change-Id: I4a28d853e730dff9b69aec9555505803cf2fcd63
2015-03-06[optimizing] Enable x86 long support.Nicolas Geoffray
Change-Id: I9006972a65a1f191c45691104a960366747f9d16
2015-03-05[optimizing] Use callee-save registers for x86Mark Mendell
Add ESI, EDI, EBP to available registers for non-baseline mode. Ensure that they aren't used when byte addressible registers are needed. Change-Id: Ie7130d4084c2ae9cfcd1e47c26eb3e5dcac1ebd6 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-02-19Ensure the graph is correctly typed.Nicolas Geoffray
We used to be forgiving because of HIntConstant(0) also being used for null. We now create a special HNullConstant for such uses. Also, we need to run the dead phi elimination twice during ssa building to ensure the correctness. Change-Id: If479efa3680d3358800aebb1cca692fa2d94f6e5
2015-02-19Have the opt. compiler set the size of "empty" frames to zero.Roland Levillain
This is to mimic Quick's behavior and honor stack frame alignment constraints after changes introduced by Change-Id I0fdb31e8c631e99091b818874a558c9aa04b1628. This issue use to make oatdump crash on oat files produced by the optimized compiler (e.g. out/host/linux-x86/framework/x86_64/core-optimizing.oat). Change-Id: I8ba52601edb0a0993eaf8923eba55aafdce5043e
2015-02-18Avoid generating jmp +0.Nicolas Geoffray
When a block branches to a non-following block, but blocks in-between do branch to it, we can avoid doing the branch. Change-Id: I9b343f662a4efc718cd4b58168f93162a24e1219
2015-02-06Optimize leaf methods.Nicolas Geoffray
Avoid suspend checks and stack changes when not needed. Change-Id: I0fdb31e8c631e99091b818874a558c9aa04b1628
2015-02-03Use a different block order when not compiling baseline.Nicolas Geoffray
Use the linearized order instead, as it puts blocks logically next to each other in a better way. Also, it does not contain dead blocks. Change-Id: Ie65b56041a093c8155e6c1e06351cb36a4053505
2015-01-24Support callee-save registers on ARM.Nicolas Geoffray
Change-Id: I7c519b7a828c9891b1141a8e51e12d6a8bc84118
2015-01-23Support callee save floating point registers on x64.Nicolas Geoffray
- Share the computation of core_spill_mask and fpu_spill_mask between backends. - Remove explicit stack overflow check support: we need to adjust them and since they are not tested, they will easily bitrot. Change-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a
2015-01-21Enable core callee-save on x64.Nicolas Geoffray
Will work on other architectures and FP support in other CLs. Change-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d